StereoscanElectronics - Revision history

Mirage335 at 13:42, 12 April 2014

2014-04-12T13:42:21Z

← Older revision		Revision as of 13:42, 12 April 2014
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	* In-phase acquisition and response.		* In-phase acquisition and response.
	* One-shot sample-and-hold behavior may be acceptable.		* One-shot sample-and-hold behavior may be acceptable.

			These requirements may be relaxed somewhat if hardware is customized to address specific problems. However, capable hardware encourages greater flexibility in software.

	==Technology==		==Technology==

2014-04-06T12:42:52Z

References

← Older revision		Revision as of 12:42, 6 April 2014
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	http://therobotfix.wordpress.com/2011/06/27/getting-started-with-spartan-3e-fpga-and-verilog/		http://therobotfix.wordpress.com/2011/06/27/getting-started-with-spartan-3e-fpga-and-verilog/

			http://embeddedmicro.com/tutorials/mojo/installing-ise

2014-04-05T18:21:30Z

References

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	http://www.ettus.com/content/files/kb/mimo_and_sync_with_usrp_updated.pdf		http://www.ettus.com/content/files/kb/mimo_and_sync_with_usrp_updated.pdf

			http://therobotfix.wordpress.com/2011/06/27/getting-started-with-spartan-3e-fpga-and-verilog/

2014-04-02T22:07:02Z

Maximum Speed, Maximum Dynamic Range ADC/DACs

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	===Maximum Speed, Maximum Dynamic Range ADC/DACs===		===Maximum Speed, Maximum Dynamic Range ADC/DACs===
	Modern audio devices can achieve approximately 120dB dynamic range at 192kHz sampling rates. The remaining 89.5dB (1V-30kV) dynamic range may be achieved through rarely switched gain programming resistors.		Modern audio devices can achieve approximately 120dB dynamic range at 192kHz sampling rates. The remaining 89.5dB (1V-30kV) dynamic range may be achieved through rarely switched gain programming resistors, or a second ADC.

	Usually these devices operate over I2S. Unfortunately, the I2S protocol requires ~4.6MHz per 24bit 192kS/s channel. Reading or driving 18 channels would require ~83MHz.		Usually these devices operate over I2S. Unfortunately, the I2S protocol requires ~4.6MHz per 24bit 192kS/s channel. Reading or driving 18 channels would require ~83MHz.

2014-04-02T21:43:01Z

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	Candidate devices include:		Candidate devices include:
	* ES9018 (Claims to be a 32-bit DAC.)		* ES9018 (Claims to be a 32-bit DAC.)

			===Maximum Resolution ADC===
			LTC2440 is ATMega32U4/Arduino compatible, and most appropriate for independent low-speed applications (ie. vacuum gauge).

			===High Performance Analog Amplifier Chips===
			Same as used in the biosignal amplifier should work here, both for low and high-impedance measurement as well as fully differential (using an instrumentation amplifier).

	==Hosts==		==Hosts==

2014-04-02T20:53:06Z

FPGA

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	Platforms under consideration:		Platforms under consideration:
	spartan3 (HacDC may already have some.)		* spartan3 (HacDC may already have some.)
	Mojo v3 FPGA Development Board		* Mojo v3 FPGA Development Board
	DE0-Nano		* DE0-Nano
	Altera DE0 Board		* Altera DE0 Board

	===USRP===		===USRP===

2014-04-02T19:15:20Z

← Older revision		Revision as of 19:15, 2 April 2014
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	Altera DE0 Board		Altera DE0 Board

	===~~Off-the-Shelf~~===		===USRP===
	Some USRP devices may be capable of real-time synchronized operation at high speed. Cost is high, dynamic range is only 16 bit, and many ferrite common-mode chokes would be needed to minimize noise.		Some USRP devices may be directly capable of real-time synchronized operation at high speed. Cost is high, dynamic range is only 16 bit, and many ferrite common-mode chokes would be needed to minimize noise.
	~~http://www.ettus.com/content/files/kb/mimo_and_sync_with_usrp_updated.pdf~~

	=References=		=References=
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	http://wiki.hacdc.org/index.php/Xilinx_ISE_Installation_Instructions		http://wiki.hacdc.org/index.php/Xilinx_ISE_Installation_Instructions

			http://www.ettus.com/content/files/kb/mimo_and_sync_with_usrp_updated.pdf

2014-04-02T18:22:47Z

← Older revision		Revision as of 18:22, 2 April 2014
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	http://opencores.com/project,minsoc		http://opencores.com/project,minsoc

			http://www2.uni-frankfurt.de/39888289/mbLinux1.pdf

			http://wiki.hacdc.org/index.php/FPGA_Workshop#FPGA_Toolchain

			http://wiki.hacdc.org/index.php/Xilinx_ISE_Installation_Instructions

2014-04-02T18:18:33Z

← Older revision		Revision as of 18:18, 2 April 2014
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	http://alvie.com/zpuino/examples.html		http://alvie.com/zpuino/examples.html

			http://opencores.com/project,minsoc

2014-04-02T18:14:49Z

← Older revision		Revision as of 18:14, 2 April 2014
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	==Technology==		==Technology==
	~~===Waveform Retrieval/Synthesis===~~
	===Maximum Speed, Maximum Dynamic Range ADC/DACs==		===Maximum Speed, Maximum Dynamic Range ADC/DACs===
	Modern audio devices can achieve approximately 120dB dynamic range at 192kHz sampling rates. The remaining 89.5dB (1V-30kV) dynamic range may be achieved through rarely switched gain programming resistors.		Modern audio devices can achieve approximately 120dB dynamic range at 192kHz sampling rates. The remaining 89.5dB (1V-30kV) dynamic range may be achieved through rarely switched gain programming resistors.

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	http://kevinmehall.net/openrisc/guide/		http://kevinmehall.net/openrisc/guide/

			https://groups.google.com/a/hacdc.org/forum/#!msg/blabber/xYpUuvXNFf8/SkhAqaHy75YJ

			http://alvie.com/zpuino/examples.html