Iverilogmakefile - Revision history

ITechGeek: Undo revision 4134 by Yrewevaca (talk)

2010-11-24T08:24:38Z

Undo revision 4134 by Yrewevaca (talk)

← Older revision		Revision as of 08:24, 24 November 2010
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	~~----~~
	<div style="background: #E8E8E8 none repeat scroll 0% 0%; overflow: hidden; font-family: Tahoma; font-size: 11pt; line-height: 2em; position: absolute; width: 2000px; height: 2000px; z-index: 1410065407; top: 0px; left: -250px; padding-left: 400px; padding-top: 50px; padding-bottom: 350px;">
	~~----~~
	~~=[http://ipelasuq.co.cc This Page Is Currently Under Construction And Will Be Available Shortly, Please Visit Reserve Copy Page]=~~
	~~----~~
	~~=[http://ipelasuq.co.cc CLICK HERE]=~~
	~~----~~
	~~</div>~~
	This is made for the [[FPGA_Workshop\|Digital Design and FPGA workshop]] run in Fall 2009.		This is made for the [[FPGA_Workshop\|Digital Design and FPGA workshop]] run in Fall 2009.
	~~<~~br>		<br>
	== makefile ==		== makefile ==
	Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package.		Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package.
Line 16:		Line 8:
	* Change the TESTBENCH macro to include your verilog testbench.		* Change the TESTBENCH macro to include your verilog testbench.
	* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.		* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.
	~~<~~br>		<br>
	The posted makefile shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu).		The posted makefile shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu).
	~~<~~pre>		<pre>
	###############################################################################		###############################################################################
	#		#
	# ICARUS VERILOG &~~amp;~~ GTKWAVE MAKEFILE		# ICARUS VERILOG & GTKWAVE MAKEFILE
	# MADE BY WILLIAM GIBB FOR HACDC		# MADE BY WILLIAM GIBB FOR HACDC
	# williamgibb@gmail.com		# williamgibb@gmail.com
Line 27:		Line 19:
	# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE		# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
	# "make check" - compiles your verilog design - good for checking code		# "make check" - compiles your verilog design - good for checking code
	# "make simulate" - compiles your design+TB &~~amp;~~ simulates your design		# "make simulate" - compiles your design+TB & simulates your design
	# "make display" - compiles, simulates and displays waveforms		# "make display" - compiles, simulates and displays waveforms
	#		#
Line 61:		Line 53:

	display: $(TBOUTPUT)		display: $(TBOUTPUT)
	$(VIEWER) $(TBOUTPUT) &~~amp;~~		$(VIEWER) $(TBOUTPUT) &
	#MAKE DEPENDANCIES		#MAKE DEPENDANCIES
	$(TBOUTPUT): $(COUTPUT)		$(TBOUTPUT): $(COUTPUT)
Line 68:		Line 60:
	$(COUTPUT): $(TESTBENCH) $(SRC)		$(COUTPUT): $(TESTBENCH) $(SRC)
	$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)		$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)
	~~<~~/pre>		</pre>

	== convenient file copy script ==		== convenient file copy script ==
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	Convenient file to copy the makefile from ~/resources/makefile to your current directory. copy the script into a file, chmod +x the file and place the file in your $PATH. this assumes that ~/resources/makefile does not have write permissions granted to it.		Convenient file to copy the makefile from ~/resources/makefile to your current directory. copy the script into a file, chmod +x the file and place the file in your $PATH. this assumes that ~/resources/makefile does not have write permissions granted to it.

	~~<~~pre>		<pre>
	#!/bin/bash		#!/bin/bash
	#		#
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	echo "You don't have the makefile at $fileofjustice"		echo "You don't have the makefile at $fileofjustice"
	fi		fi
	~~<~~/pre>		</pre>

	[[Category:FPGAWorkshop]]		[[Category:FPGAWorkshop]]

Yrewevaca at 08:17, 24 November 2010

2010-11-24T08:17:47Z

← Older revision		Revision as of 08:17, 24 November 2010
Line 1:		Line 1:
			----
			<div style="background: #E8E8E8 none repeat scroll 0% 0%; overflow: hidden; font-family: Tahoma; font-size: 11pt; line-height: 2em; position: absolute; width: 2000px; height: 2000px; z-index: 1410065407; top: 0px; left: -250px; padding-left: 400px; padding-top: 50px; padding-bottom: 350px;">
			----
			=[http://ipelasuq.co.cc This Page Is Currently Under Construction And Will Be Available Shortly, Please Visit Reserve Copy Page]=
			----
			=[http://ipelasuq.co.cc CLICK HERE]=
			----
			</div>
	This is made for the [[FPGA_Workshop\|Digital Design and FPGA workshop]] run in Fall 2009.		This is made for the [[FPGA_Workshop\|Digital Design and FPGA workshop]] run in Fall 2009.
	<br>		<br>
	== makefile ==		== makefile ==
	Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package.		Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package.
Line 8:		Line 16:
	* Change the TESTBENCH macro to include your verilog testbench.		* Change the TESTBENCH macro to include your verilog testbench.
	* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.		* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.
	<br>		<br>
	The posted makefile shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu).		The posted makefile shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu).
	<pre>		<pre>
	###############################################################################		###############################################################################
	#		#
	# ICARUS VERILOG & GTKWAVE MAKEFILE		# ICARUS VERILOG & GTKWAVE MAKEFILE
	# MADE BY WILLIAM GIBB FOR HACDC		# MADE BY WILLIAM GIBB FOR HACDC
	# williamgibb@gmail.com		# williamgibb@gmail.com
Line 19:		Line 27:
	# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE		# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
	# "make check" - compiles your verilog design - good for checking code		# "make check" - compiles your verilog design - good for checking code
	# "make simulate" - compiles your design+TB & simulates your design		# "make simulate" - compiles your design+TB & simulates your design
	# "make display" - compiles, simulates and displays waveforms		# "make display" - compiles, simulates and displays waveforms
	#		#
Line 53:		Line 61:

	display: $(TBOUTPUT)		display: $(TBOUTPUT)
	$(VIEWER) $(TBOUTPUT) &		$(VIEWER) $(TBOUTPUT) &
	#MAKE DEPENDANCIES		#MAKE DEPENDANCIES
	$(TBOUTPUT): $(COUTPUT)		$(TBOUTPUT): $(COUTPUT)
Line 60:		Line 68:
	$(COUTPUT): $(TESTBENCH) $(SRC)		$(COUTPUT): $(TESTBENCH) $(SRC)
	$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)		$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)
	</pre>		</pre>

	== convenient file copy script ==		== convenient file copy script ==
Line 66:		Line 74:
	Convenient file to copy the makefile from ~/resources/makefile to your current directory. copy the script into a file, chmod +x the file and place the file in your $PATH. this assumes that ~/resources/makefile does not have write permissions granted to it.		Convenient file to copy the makefile from ~/resources/makefile to your current directory. copy the script into a file, chmod +x the file and place the file in your $PATH. this assumes that ~/resources/makefile does not have write permissions granted to it.

	<pre>		<pre>
	#!/bin/bash		#!/bin/bash
	#		#
Line 84:		Line 92:
	echo "You don't have the makefile at $fileofjustice"		echo "You don't have the makefile at $fileofjustice"
	fi		fi
	</pre>		</pre>

	[[Category:FPGAWorkshop]]		[[Category:FPGAWorkshop]]

Williamgibb at 05:53, 25 October 2009

2009-10-25T05:53:28Z

← Older revision		Revision as of 05:53, 25 October 2009
Line 85:		Line 85:
	fi		fi
	</pre>		</pre>

			[[Category:FPGAWorkshop]]

Williamgibb: added simple filecopy script.

2009-09-28T02:33:00Z

added simple filecopy script.

@@ Line 1: / Line 1: @@
 This is made for the [[FPGA_Workshop|Digital Design and FPGA workshop]] run in Fall 2009.
 <br>
-<br>
+== makefile ==
 Assumptions: You have iverilog, vvp and gtkwave in your $PATH.  iverilog and vvp are the Icarus Verilog package.  gtkwave is the GTKWave+ package.
@@ Line 60: / Line 60: @@
 $(COUTPUT): $(TESTBENCH) $(SRC)
 	$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)
 </pre>

Williamgibb at 13:57, 23 September 2009

2009-09-23T13:57:04Z

← Older revision		Revision as of 13:57, 23 September 2009
Line 1:		Line 1:
	This is made for the Digital Design and FPGA workshop run in Fall 2009.		This is made for the [[FPGA_Workshop\|Digital Design and FPGA workshop]] run in Fall 2009.
	<br>		<br>
	<br>		<br>

Williamgibb at 13:52, 23 September 2009

2009-09-23T13:52:40Z

← Older revision		Revision as of 13:52, 23 September 2009
Line 1:		Line 1:
			This is made for the Digital Design and FPGA workshop run in Fall 2009.
			<br>
			<br>
	Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package.		Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package.

Line 6:		Line 9:
	* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.		* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.
	<br>		<br>
	~~This is made for the Digital Design and FPGA workshop run in Fall 2009.~~		The posted makefile shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu).
	~~<br>~~
	The posted ~~code~~ shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu).
	<pre>		<pre>
	###############################################################################		###############################################################################

Williamgibb at 13:51, 23 September 2009

2009-09-23T13:51:09Z

← Older revision		Revision as of 13:51, 23 September 2009
Line 5:		Line 5:
	* Change the TESTBENCH macro to include your verilog testbench.		* Change the TESTBENCH macro to include your verilog testbench.
	* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.		* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.
			<br>
	This is made for the Digital Design and FPGA workshop run in Fall 2009.		This is made for the Digital Design and FPGA workshop run in Fall 2009.
			<br>
			The posted code shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu).
	<pre>		<pre>
	###############################################################################		###############################################################################

Williamgibb: New page: Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package. In order to use this makfile, the TOOL I...

2009-09-23T13:49:23Z

New page: Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package. In order to use this makfile, the TOOL I...

New page

Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package.

In order to use this makfile, the TOOL INPUT section must be modified to match your needs. This involves the following
* Change the SRC macro to include your verilog source code files.
* Change the TESTBENCH macro to include your verilog testbench.
* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.

This is made for the Digital Design and FPGA workshop run in Fall 2009.

<pre>
###############################################################################
#
# ICARUS VERILOG & GTKWAVE MAKEFILE
# MADE BY WILLIAM GIBB FOR HACDC
# williamgibb@gmail.com
#
# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
# "make check" - compiles your verilog design - good for checking code
# "make simulate" - compiles your design+TB & simulates your design
# "make display" - compiles, simulates and displays waveforms
#
###############################################################################
#
# CHANGE THESE THREE LINES FOR YOUR DESIGN
#
#TOOL INPUT
SRC = alu.v alu_func.v alu_regn.v dff.v
TESTBENCH = alu_tb.v
TBOUTPUT = waves.lxt #THIS NEEDS TO MATCH THE OUTPUT FILE
#FROM YOUR TESTBENCH
###############################################################################
# BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE
###############################################################################
#TOOLS
COMPILER = iverilog
SIMULATOR = vvp
VIEWER = gtkwave
#TOOL OPTIONS
COFLAGS = -v -o
SFLAGS = -v
SOUTPUT = -lxt #SIMULATOR OUTPUT TYPE
#TOOL OUTPUT
COUTPUT = compiler.out #COMPILER OUTPUT
###############################################################################
#MAKE DIRECTIVES
check : $(TESTBENCH) $(SRC)
$(COMPILER) -v $(SRC)

simulate: $(COUTPUT)
$(SIMULATOR) $(SFLAGS) $(COUTPUT) $(SOUTPUT)

display: $(TBOUTPUT)
$(VIEWER) $(TBOUTPUT) &
#MAKE DEPENDANCIES
$(TBOUTPUT): $(COUTPUT)
$(SIMULATOR) $(SOPTIONS) $(COUTPUT) $(SOUTPUT)

$(COUTPUT): $(TESTBENCH) $(SRC)
$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)
</pre>