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	<id>https://old.hacdc.org/index.php?action=history&amp;feed=atom&amp;title=FPGAWorkshopMaitland</id>
	<title>FPGAWorkshopMaitland - Revision history</title>
	<link rel="self" type="application/atom+xml" href="https://old.hacdc.org/index.php?action=history&amp;feed=atom&amp;title=FPGAWorkshopMaitland"/>
	<link rel="alternate" type="text/html" href="https://old.hacdc.org/index.php?title=FPGAWorkshopMaitland&amp;action=history"/>
	<updated>2026-05-07T14:23:02Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
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	<entry>
		<id>https://old.hacdc.org/index.php?title=FPGAWorkshopMaitland&amp;diff=6748&amp;oldid=prev</id>
		<title>ITechGeek at 17:06, 3 April 2012</title>
		<link rel="alternate" type="text/html" href="https://old.hacdc.org/index.php?title=FPGAWorkshopMaitland&amp;diff=6748&amp;oldid=prev"/>
		<updated>2012-04-03T17:06:05Z</updated>

		<summary type="html">&lt;p&gt;&lt;/p&gt;
&lt;table style=&quot;background-color: #fff; color: #202122;&quot; data-mw=&quot;interface&quot;&gt;
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				&lt;td colspan=&quot;2&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;← Older revision&lt;/td&gt;
				&lt;td colspan=&quot;2&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;Revision as of 17:06, 3 April 2012&lt;/td&gt;
				&lt;/tr&gt;&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot; id=&quot;mw-diff-left-l1&quot;&gt;Line 1:&lt;/td&gt;
&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Line 1:&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-side-deleted&quot;&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot; data-marker=&quot;+&quot;&gt;&lt;/td&gt;&lt;td style=&quot;color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;[[Category:FPGAWorkshop]]&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-side-deleted&quot;&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot; data-marker=&quot;+&quot;&gt;&lt;/td&gt;&lt;td style=&quot;color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;1. Port [http://amrad.org/projects/charleston_sdr/ &amp;#039;&amp;#039;&amp;#039;AMRAD Charleston&amp;#039;&amp;#039;&amp;#039;] FPGA loads from Digilent Nexys2 to the Xilinx Spartan3 dev board&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;1. Port [http://amrad.org/projects/charleston_sdr/ &amp;#039;&amp;#039;&amp;#039;AMRAD Charleston&amp;#039;&amp;#039;&amp;#039;] FPGA loads from Digilent Nexys2 to the Xilinx Spartan3 dev board&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;br/&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;br/&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/table&gt;</summary>
		<author><name>ITechGeek</name></author>
	</entry>
	<entry>
		<id>https://old.hacdc.org/index.php?title=FPGAWorkshopMaitland&amp;diff=2660&amp;oldid=prev</id>
		<title>Maitland: Maitland&#039;s SDR investigations</title>
		<link rel="alternate" type="text/html" href="https://old.hacdc.org/index.php?title=FPGAWorkshopMaitland&amp;diff=2660&amp;oldid=prev"/>
		<updated>2009-12-23T21:26:28Z</updated>

		<summary type="html">&lt;p&gt;Maitland&amp;#039;s SDR investigations&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;1. Port [http://amrad.org/projects/charleston_sdr/ &amp;#039;&amp;#039;&amp;#039;AMRAD Charleston&amp;#039;&amp;#039;&amp;#039;] FPGA loads from Digilent Nexys2 to the Xilinx Spartan3 dev board&lt;br /&gt;
&lt;br /&gt;
2. See if [http://plausible.org/andy/nexys2prog.tar.gz &amp;#039;&amp;#039;&amp;#039;nexsys2prog&amp;#039;&amp;#039;&amp;#039;] can be adapted to support these boards and allow [http://packages.debian.org/squeeze/urjtag &amp;#039;&amp;#039;&amp;#039;UrJTAG&amp;#039;&amp;#039;&amp;#039;] to work.&lt;br /&gt;
&lt;br /&gt;
3. Try to mimic a USRP only using AMRAD Charleston receiver boards. (Or audio ADC.)&lt;br /&gt;
&lt;br /&gt;
4. Look into [http://www.digitalif.org/ &amp;#039;&amp;#039;&amp;#039;VITA Radio Transport (VRT) protocol&amp;#039;&amp;#039;&amp;#039;] support&lt;br /&gt;
&lt;br /&gt;
5. Make use of the Ethernet port, possibly mimic a USRP2.&lt;/div&gt;</summary>
		<author><name>Maitland</name></author>
	</entry>
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