FPGAWeek12Exercise - Revision history

Williamgibb at 01:59, 6 January 2010

2010-01-06T01:59:08Z

← Older revision		Revision as of 01:59, 6 January 2010
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	*** Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder		*** Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder
	*** A portion of the design uses a undocumented mode of operation for the S3E DCM. Instructions for enabling this can be found in the dcm_fixed_osc.vhd file. In my experience, this breaks P&R (-will), and this should be removed in order to complete the design. The DCM is simply working in an free-running oscillator mode; this is merely used to provide a frequency source for testing and its removal will not adversely affect the design.		*** A portion of the design uses a undocumented mode of operation for the S3E DCM. Instructions for enabling this can be found in the dcm_fixed_osc.vhd file. In my experience, this breaks P&R (-will), and this should be removed in order to complete the design. The DCM is simply working in an free-running oscillator mode; this is merely used to provide a frequency source for testing and its removal will not adversely affect the design.
	**** You'll need to modify the frequency_counter.vhd file in the project, to remove the instance of 'dcm_fixed_osc.vhd' from the design. We won't be doing anything in-depth with VHDL so don't be intimidated by the different language syntax.		**** You'll need to modify the '''frequency_counter.vhd''' file in the project, to remove the instance of 'dcm_fixed_osc.vhd' from the design. We won't be doing anything in-depth with VHDL so don't be intimidated by the different language syntax.
	**** You'll want to comment out the component dcm_fixed_osc (approx line 117) . In VHDL, comments are done with double hypens, --.		**** You'll want to comment out the component dcm_fixed_osc (approx line 117) . In VHDL, comments are done with double hypens, --.
	**** Commented out component		**** Commented out component

Obscurite at 01:49, 6 January 2010

2010-01-06T01:49:13Z

← Older revision		Revision as of 01:49, 6 January 2010
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	freq_for_measurement <= sma_clk when (source_control(1 downto 0)="00")		freq_for_measurement <= sma_clk when (source_control(1 downto 0)="00")
	else clk_50mhz when (source_control(1 downto 0)="01")		else clk_50mhz when (source_control(1 downto 0)="01")
	else ~~'''ring'''_oscillator~~ when (source_control(1 downto 0)="10")		else ring_oscillator when (source_control(1 downto 0)="10")
	else ring_oscillator;		else ring_oscillator;
	</pre>		</pre>

Obscurite at 01:48, 6 January 2010

2010-01-06T01:48:49Z

← Older revision		Revision as of 01:48, 6 January 2010
Line 39:		Line 39:
	freq_for_measurement <= sma_clk when (source_control(1 downto 0)="00")		freq_for_measurement <= sma_clk when (source_control(1 downto 0)="00")
	else clk_50mhz when (source_control(1 downto 0)="01")		else clk_50mhz when (source_control(1 downto 0)="01")
	else ~~ring_oscillator~~ when (source_control(1 downto 0)="10")		else '''ring'''_oscillator when (source_control(1 downto 0)="10")
	else ring_oscillator;		else ring_oscillator;
	</pre>		</pre>

Williamgibb at 15:46, 5 January 2010

2010-01-05T15:46:39Z

← Older revision		Revision as of 15:46, 5 January 2010
Line 49:		Line 49:
	*** Add the existing .vhd and .ucf sources from the frequency ref reference design folder that you unzipped		*** Add the existing .vhd and .ucf sources from the frequency ref reference design folder that you unzipped
	*** Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder		*** Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder
	*** A portion of the design uses a undocumented mode of operation for the S3E DCM. Instructions for enabling this can be found on page 13 of the Frequency generator documentation.		*** A portion of the design uses a undocumented mode of operation for the S3E DCM. Instructions for enabling this can be found on page 13 of the Frequency generator documentation. '''The design will not work if the instructions are not followed!'''
	*** Afer this is done, you should be able to implement this design and program the FPGA with impact.		*** Afer this is done, you should be able to implement this design and program the FPGA with impact.
	* Things you can do!		* Things you can do!

Williamgibb at 15:45, 5 January 2010

2010-01-05T15:45:54Z

← Older revision		Revision as of 15:45, 5 January 2010
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	-- kick_start => source_control(7) );		-- kick_start => source_control(7) );
	</pre>		</pre>
	**** Now we'll need to change the multiplexer. To keep the design nearly intact, we'll replicate the ring oscillator signal twice.		**** Now we'll need to change the multiplexer. To keep the design nearly intact, we'll replicate the ring oscillator signal twice (approx line 245).
	**** Changed multiplexer		**** Changed multiplexer
	<pre>		<pre>

Williamgibb at 15:44, 5 January 2010

2010-01-05T15:44:58Z

@@ Line 1: / Line 1: @@
 * Download the Frequency Counter and Frequency Generator reference designs from http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm
 * Download the Picoblaze processor core from http://www.xilinx.com/products/ipcenter/picoblaze-S3-V2-Pro.htm
@@ Line 15: / Line 14: @@
 *** A portion of the design uses a undocumented mode of operation for the S3E DCM.  Instructions for enabling this can be found in the dcm_fixed_osc.vhd file.  In my experience, this breaks P&R (-will), and this should be removed in order to complete the design.  The DCM is simply working in an free-running oscillator mode; this is merely used to provide a frequency source for testing and its removal will not adversely affect the design.
 **** You'll need to modify the frequency_counter.vhd file in the project, to remove the instance of 'dcm_fixed_osc.vhd' from the design.  We won't be doing anything in-depth with VHDL so don't be intimidated by the different language syntax.
-****
+**** You'll want to comment out the component dcm_fixed_osc (approx line 117) .  In VHDL, comments are done with double hypens, --.
-****
+**** Commented out component
 *** Select the top level module, and take it through the implementation process - synthesis, place and route, generate programming file.
 *** Use impact to program the .bit file to the FPGA!  It should
@@ Line 26: / Line 51: @@
 *** A portion of the design uses a undocumented mode of operation for the S3E DCM.  Instructions for enabling this can be found on page 13 of the Frequency generator documentation.
 *** Afer this is done, you should be able to implement this design and program the FPGA with impact.
-* Make a frequency counter board read the frequency generated by another board!
+* Things you can do!
-** We'll need to move the input to the
+** You can use the .ucf file to move around the pin assignments.  For instance, you can have the frequency counter read the clock input off of a stake or one of the pmod headers.3
+** Easy extension - create a second ring oscillator, called ring_osc2.  You can extend the ring_osc.vhd for this purpose, adding additional delay stages will decrease the frequency generated.  Follow a similar format, to the rest of the VHDL code, to declare the component, instantiation, a second ring_oscillator signal, and modify the multiplexer.
 [[Category:FPGAWorkshop]]

Williamgibb at 13:58, 5 January 2010

2010-01-05T13:58:21Z

← Older revision		Revision as of 13:58, 5 January 2010
Line 5:		Line 5:
	* Implementing the projects directly		* Implementing the projects directly
	** Each project comes with a .bit file that you can use to program the FPGA starter kit with. Use impact to program the chip.		** Each project comes with a .bit file that you can use to program the FPGA starter kit with. Use impact to program the chip.
	** On Windows, you can run the install batch scripts to run impact automatically		** On Windows, you can run the install batch scripts to run impact automatically.
			** Find a buddy with a board, and each of you program your respective boards. Grab an SMA cable and use that to check the output of the generator with the counter.
	* Implementing the projects through ISE		* Implementing the projects through ISE
	** Implementing the frequency counter		** Implementing the frequency counter
Line 12:		Line 13:
	*** Add the existing .vhd and .ucf sources from the frequency counter reference design folder that you unzipped		*** Add the existing .vhd and .ucf sources from the frequency counter reference design folder that you unzipped
	*** Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder		*** Add the existing .vhd source for kcpsm3.vhd from the picoblaze VHDL source folder
	*** A portion of the design uses a undocumented mode of operation for the S3E DCM. Instructions for enabling this can be found in the dcm_fixed_osc.vhd file. ~~They are excerpted as follows:~~		*** A portion of the design uses a undocumented mode of operation for the S3E DCM. Instructions for enabling this can be found in the dcm_fixed_osc.vhd file. In my experience, this breaks P&R (-will), and this should be removed in order to complete the design. The DCM is simply working in an free-running oscillator mode; this is merely used to provide a frequency source for testing and its removal will not adversely affect the design.
	**** This design is ~~for SPARTAN~~-~~3E devices only. Special set up required~~ to ~~process this~~ design ~~with ISE tools~~.		**** You'll need to modify the frequency_counter.vhd file in the project, to remove the instance of 'dcm_fixed_osc.vhd' from the design. We won't be doing anything in-depth with VHDL so don't be intimidated by the different language syntax.
	**** ~~On Windows: Set an environment variable called XIL_TEST_ARCS - My_computer -> properties -> advanced -> Environment variables~~ ~~System variables~~ -~~> New -> XIL_TEST_ARCS~~ with ~~value = 1 - Make sure~~ the ~~Xilinx tools are closed and opened again before using~~.		****
	*** ~~Once the variable has been set, close ISE and restart it.~~		****
	*** Select the top level module, and take it through the implementation process - synthesis, place and route, generate programming file.		*** Select the top level module, and take it through the implementation process - synthesis, place and route, generate programming file.
	*** Use impact to program the .bit file to the FPGA! It should		*** Use impact to program the .bit file to the FPGA! It should

Williamgibb at 15:29, 4 January 2010

2010-01-04T15:29:53Z

← Older revision		Revision as of 15:29, 4 January 2010
Line 1:		Line 1:
			''' These are currently incomplete & need to be reviewed - use at your own risk '''
	* Download the Frequency Counter and Frequency Generator reference designs from http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm		* Download the Frequency Counter and Frequency Generator reference designs from http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm
	* Download the Picoblaze processor core from http://www.xilinx.com/products/ipcenter/picoblaze-S3-V2-Pro.htm		* Download the Picoblaze processor core from http://www.xilinx.com/products/ipcenter/picoblaze-S3-V2-Pro.htm

Obscurite at 04:01, 31 December 2009

2009-12-31T04:01:44Z

← Older revision		Revision as of 04:01, 31 December 2009
Line 1:		Line 1:
	* Download the Frequency Counter and Frequency Generator reference designs from http://www.xilinx.com/products/boards/s3estarter\/reference_designs.htm		* Download the Frequency Counter and Frequency Generator reference designs from http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm
	* Download the Picoblaze processor core from http://www.xilinx.com/products/ipcenter/picoblaze-S3-V2-Pro.htm		* Download the Picoblaze processor core from http://www.xilinx.com/products/ipcenter/picoblaze-S3-V2-Pro.htm
	* Unzip these projects & picoblaze source to your ~/Projects directory (or appropriatlely)		* Unzip these projects & picoblaze source to your ~/Projects directory (or appropriatlely)

Williamgibb at 02:47, 31 December 2009

2009-12-31T02:47:45Z

← Older revision		Revision as of 02:47, 31 December 2009
Line 24:		Line 24:
	*** A portion of the design uses a undocumented mode of operation for the S3E DCM. Instructions for enabling this can be found on page 13 of the Frequency generator documentation.		*** A portion of the design uses a undocumented mode of operation for the S3E DCM. Instructions for enabling this can be found on page 13 of the Frequency generator documentation.
	*** Afer this is done, you should be able to implement this design and program the FPGA with impact.		*** Afer this is done, you should be able to implement this design and program the FPGA with impact.
	** asdf		* Make a frequency counter board read the frequency generated by another board!
	** asdf		** We'll need to move the input to the
	** ~~asdf~~


	[[Category:FPGAWorkshop]]		[[Category:FPGAWorkshop]]