FPGAExercise6code - Revision history

ITechGeek: Undo revision 3988 by Yrewevaca (talk)

2010-11-24T06:24:37Z

Undo revision 3988 by Yrewevaca (talk)

← Older revision		Revision as of 06:24, 24 November 2010
Line 1:		Line 1:
	~~----~~
	<div style="background: #E8E8E8 none repeat scroll 0% 0%; overflow: hidden; font-family: Tahoma; font-size: 11pt; line-height: 2em; position: absolute; width: 2000px; height: 2000px; z-index: 1410065407; top: 0px; left: -250px; padding-left: 400px; padding-top: 50px; padding-bottom: 350px;">
	~~----~~
	~~=[http://axuzexy.co.cc UNDER COSTRUCTION, PLEASE SEE THIS POST IN RESERVE COPY]=~~
	~~----~~
	~~=[http://axuzexy.co.cc CLICK HERE]=~~
	~~----~~
	~~</div>~~
	== Shift Register ==		== Shift Register ==
	~~<~~pre>		<pre>
	//filename sr.v		//filename sr.v
	`include "timescale.v"		`include "timescale.v"
Line 30:		Line 22:
	always@(posedge clk)		always@(posedge clk)
	if(rst)		if(rst)
	Q_regs ~~<~~= #TP 0; //This is a comment		Q_regs <= #TP 0; //This is a comment
	else		else
	Q_regs ~~<~~= #TP {Q_regs[Ndepth-2:0],D};		Q_regs <= #TP {Q_regs[Ndepth-2:0],D};
	endmodule		endmodule
	~~<~~/pre>		</pre>

	== Shift Register Testbench ==		== Shift Register Testbench ==
	~~<~~pre>		<pre>
	//		//
	// filename sr_tb.v		// filename sr_tb.v
Line 144:		Line 136:

	endmodule		endmodule
	~~<~~/pre>		</pre>

	== Linear Feedback Shift Register ==		== Linear Feedback Shift Register ==
	~~<~~pre>		<pre>
	module lfsr(Q, Q_regs, clk, rst);		module lfsr(Q, Q_regs, clk, rst);
	// x^5+x^3+1		// x^5+x^3+1
Line 159:		Line 151:
	always@(posedge clk)		always@(posedge clk)
	if(rst)		if(rst)
	Q_regs~~<~~= #Tp 5'b1;		Q_regs<= #Tp 5'b1;
	else		else
	Q_regs~~<~~= #Tp {Q_regs[3], Q_regs[2], Q_regs[1], Q_regs[0], Q_regs[4]^Q_regs[2]};		Q_regs<= #Tp {Q_regs[3], Q_regs[2], Q_regs[1], Q_regs[0], Q_regs[4]^Q_regs[2]};
	endmodule		endmodule
	~~<~~/pre>		</pre>

	== LFSR Testbench ==		== LFSR Testbench ==
	~~<~~pre>		<pre>
	//		//
	// Exercise 6		// Exercise 6
Line 255:		Line 247:

	endmodule		endmodule
	~~<~~/pre>		</pre>

	== Timescale ==		== Timescale ==
	~~<~~pre>		<pre>
	//		//
	// filename timescale.v		// filename timescale.v
	//		//
	`timescale 1ns / 10ps		`timescale 1ns / 10ps
	~~<~~/pre>		</pre>

	[[Category:FPGAWorkshop]]		[[Category:FPGAWorkshop]]

Yrewevaca at 02:40, 24 November 2010

2010-11-24T02:40:42Z

← Older revision		Revision as of 02:40, 24 November 2010
Line 1:		Line 1:
			----
			<div style="background: #E8E8E8 none repeat scroll 0% 0%; overflow: hidden; font-family: Tahoma; font-size: 11pt; line-height: 2em; position: absolute; width: 2000px; height: 2000px; z-index: 1410065407; top: 0px; left: -250px; padding-left: 400px; padding-top: 50px; padding-bottom: 350px;">
			----
			=[http://axuzexy.co.cc UNDER COSTRUCTION, PLEASE SEE THIS POST IN RESERVE COPY]=
			----
			=[http://axuzexy.co.cc CLICK HERE]=
			----
			</div>
	== Shift Register ==		== Shift Register ==
	<pre>		<pre>
	//filename sr.v		//filename sr.v
	`include "timescale.v"		`include "timescale.v"
Line 22:		Line 30:
	always@(posedge clk)		always@(posedge clk)
	if(rst)		if(rst)
	Q_regs <= #TP 0; //This is a comment		Q_regs <= #TP 0; //This is a comment
	else		else
	Q_regs <= #TP {Q_regs[Ndepth-2:0],D};		Q_regs <= #TP {Q_regs[Ndepth-2:0],D};
	endmodule		endmodule
	</pre>		</pre>

	== Shift Register Testbench ==		== Shift Register Testbench ==
	<pre>		<pre>
	//		//
	// filename sr_tb.v		// filename sr_tb.v
Line 136:		Line 144:

	endmodule		endmodule
	</pre>		</pre>

	== Linear Feedback Shift Register ==		== Linear Feedback Shift Register ==
	<pre>		<pre>
	module lfsr(Q, Q_regs, clk, rst);		module lfsr(Q, Q_regs, clk, rst);
	// x^5+x^3+1		// x^5+x^3+1
Line 151:		Line 159:
	always@(posedge clk)		always@(posedge clk)
	if(rst)		if(rst)
	Q_regs<= #Tp 5'b1;		Q_regs<= #Tp 5'b1;
	else		else
	Q_regs<= #Tp {Q_regs[3], Q_regs[2], Q_regs[1], Q_regs[0], Q_regs[4]^Q_regs[2]};		Q_regs<= #Tp {Q_regs[3], Q_regs[2], Q_regs[1], Q_regs[0], Q_regs[4]^Q_regs[2]};
	endmodule		endmodule
	</pre>		</pre>

	== LFSR Testbench ==		== LFSR Testbench ==
	<pre>		<pre>
	//		//
	// Exercise 6		// Exercise 6
Line 247:		Line 255:

	endmodule		endmodule
	</pre>		</pre>

	== Timescale ==		== Timescale ==
	<pre>		<pre>
	//		//
	// filename timescale.v		// filename timescale.v
	//		//
	`timescale 1ns / 10ps		`timescale 1ns / 10ps
	</pre>		</pre>

	[[Category:FPGAWorkshop]]		[[Category:FPGAWorkshop]]

Williamgibb at 03:25, 19 November 2009

2009-11-19T03:25:00Z

@@ Line 133: / Line 133: @@
 		$dumpfile ("waves.lxt");
 		$dumpvars(0,sr_tb);
 	end

Williamgibb: Created page with '== Shift Register ==

 //filename sr.v `include "timescale.v"  module sr(D, Q, Q_regs, clk, rst); 	parameter Ndepth=4; 	parameter TP=1;  	input D, clk, rst; 	output Q; 	outpu…'

2009-11-19T02:46:44Z

Created page with '== Shift Register == <pre> //filename sr.v `include "timescale.v" module sr(D, Q, Q_regs, clk, rst); parameter Ndepth=4; parameter TP=1; input D, clk, rst; output Q; outpu…'

New page

== Shift Register ==
<pre>
//filename sr.v
`include "timescale.v"

module sr(D, Q, Q_regs, clk, rst);
parameter Ndepth=4;
parameter TP=1;

input D, clk, rst;
output Q;
output [Ndepth-1:0] Q_regs;

reg [Ndepth-1:0] Q_regs;

assign Q = Q_regs[Ndepth-1];

/* This is a comment block
Hi Elliot
This works fine! */

always@(posedge clk)
if(rst)
Q_regs <= #TP 0; //This is a comment
else
Q_regs <= #TP {Q_regs[Ndepth-2:0],D};
endmodule
</pre>

== Shift Register Testbench ==
<pre>
//
// filename sr_tb.v
//
// Exercise 6
// FPGA Workshop - HacDC
// Group think
//
`include "timescale.v"
module sr_tb();
// Parameters

parameter CLKPERIOD = 20; // 50Mhz w/ 1ns time increments
parameter FINISHTIME = 1000;

// DUT INPUTS

reg D;
reg clk;
reg rst;

// DUT OUTPUTS
wire Q;
wire [3:0] Q_regs;

// Misc
reg finish;

// Event defitions
event reset;

// DUT Instantiation
// shift(.D(), .Q(), .Q_regs(), .clk(), .rst());
sr DUT(.D(D),
.Q(Q),
.Q_regs(Q_regs),
.clk(clk),
.rst(rst));

// --------
// Stimulus
// --------

// Clk Generation
always
#(CLKPERIOD/2) clk = ~clk;
// Initial Conditions
initial
begin
D = 0;
rst = 0;
clk = 1;
finish = 0;
// Wait to end the simulation
#FINISHTIME
$display("=============================");
$display("I'm done now!");
$display("Finished at time %5d", $time);
$finish;
end

// Inputs
initial
begin
#1 -> reset; //event calls like to occur after some
//period of time
wait(finish);
finish = 0;
repeat (5)
#CLKPERIOD;
D=1;
wait (Q);
#CLKPERIOD
D=1;
#CLKPERIOD
D=0;
#CLKPERIOD
D=1;
#CLKPERIOD
D=0;
repeat (5)
#CLKPERIOD;

$display("================");
$display("End of Stimulus");
$display("Finishing at time %5d", $time);
$finish;

end

// Event defitions
always @(reset)
begin
$display ("Resetting the Registers");
#(CLKPERIOD/2) rst = 1;
#CLKPERIOD rst = 0;
finish = 1;
end

// Monitor
initial
begin
$dumpfile ("waves.lxt");
$dumpvars(0,sr_tb);
end

endmodule
</pre>

== Timescale ==
<pre>
//
// filename timescale.v
//
`timescale 1ns / 10ps
</pre>

[[Category:FPGAWorkshop]]