HacDC Wiki - User contributions [en]

FPGAWorkshopMaitland

2009-12-23T21:26:28Z

Maitland: Maitland's SDR investigations

1. Port [http://amrad.org/projects/charleston_sdr/ '''AMRAD Charleston'''] FPGA loads from Digilent Nexys2 to the Xilinx Spartan3 dev board

2. See if [http://plausible.org/andy/nexys2prog.tar.gz '''nexsys2prog'''] can be adapted to support these boards and allow [http://packages.debian.org/squeeze/urjtag '''UrJTAG'''] to work.

3. Try to mimic a USRP only using AMRAD Charleston receiver boards. (Or audio ADC.)

4. Look into [http://www.digitalif.org/ '''VITA Radio Transport (VRT) protocol'''] support

5. Make use of the Ethernet port, possibly mimic a USRP2.

FPGA Workshop

2009-12-23T21:02:43Z

Maitland: /* FPGA Workshop Projects */

== Main Topics ==
1) Introduction to digital logic & design 
2) Verilog HDL modeling & testing 
3) FPGA's & using them. 
 
We will be taking an approach of reviewing & learning digital design, implementing designs and methods of formally simulating and verifying designs before moving into [http://en.wikipedia.org/wiki/Field-programmable_gate_array FPGA] oriented work. This workshop will be more engineering oriented than hobbyist/tinkerer oriented.

== Hardware ==
We'll be covering some FPGA specific topics and projects using real hardware. The first half of the workshop will cover logic design, implementation and testing. This will allow people to put off ordering any hardware until they know that they actually want to pursue FPGA development, since the dev board I've chosen for this is not cheap but I feel is robust enough to be a good starting board for this group.
 
The hardware we'll be using is the Xilinx Spartan 3AN development kit. This kit is available from a few vendors for 199USD + shipping. This will be discussed more later on. The kit includes programming cable, and evaluation copies of some of the Xilinx tools."

== Tools ==

=== Verilog Simulation and Waveform Viewing ===
Icarus verilog & gtkwave; for doing Verilog compilation, simulation and waveform viewing. A makefile has been made to simplify the flow for any exercises and projects we use these tools with. That makefile can be found [[iverilogmakefile|'''here''']]. Instructions for installing these programs on Mac osX and Ubuntu can be found here: [[FOSS_Verilog_tool_installation | '''FOSS Verilog tool installation''']] 
=== FPGA Toolchain ===
After we finish up with covering Verilog modeling, we'll move to the Xilinx ISE Webpack tools and actual work with FPGAs. This software is available from Xilinx for free, and is available for Windows and Linux platforms. This will be used for Verilog compilation, simulation, synthesis of designs, design mapping, place and routing of designs, bitstream generation and board programming. Instructions for installing the Xilinx tools on the VM can be found here:[[Xilinx_ISE_Installation_Instructions | '''Xilinx ISE Installation Instructions''']] 
=== Virtual Machine ===
An OpenSuse Virtual Machine (VMWare based) will be available for people to use in this course, if they wish. This will
have the icarus verilog tools and GTKwave loaded on it, along with Firefox, gcc and make. The suseStudio team has encouraged the use of their VMs in such a manner (teaching workshops). This is being built in susestudio, and will be available as a live install as well.
 
When we move over to the Xilinx tools, people will have to download and install the Xilinx tools by themselves, since that material is copyrighted. Instructions will be given for doing that.

The VMware VM image is ready (ver 0.5.2) for people to grab if they wish. [http://susestudio.com/download/d931a0f28972e3505eacf8d0bad28fc0/Digital_Design__FPGA_Workshop_VM_v4.i686-0.5.2.vmx.tar.gz '''Get it here.''']

The image also works with VirtualBox. Create a new machine, and when it asks you for a hard drive, select use an existing drive. This takes you to the hard-drives list dialog box. From there, file..create a new drive, link it to the .vmdk file, select it, and you're all set. For the rest, all defaults are ok. (Bother Elliot for hints with VBox.)

There are a few items of note regarding the VM 
* Download is approximately 350MB, the tarball is about 1.5GB in size, and the virtual disk will expand up to 20gigs dynamically.
* The download link is a virgin, freshly built VM, so you'll be the first user booting it up since build.
* There are two users, root and workshop. Both have the password 'linux'
* For the user workshop, ~/scripts/ is included in their $PATH
* Also, user workshop has a few small files in ~/resources/ including a simple upcounter design example.
* May need to run the network configuration tools to ensure you get functional networking. I've experienced issues with the VM in suspend mode, switching networks on the host machine, and completely loosing network on the VM until rerunning the network config tools. They can be found poking around in the system settings for yast.
* Currently, the Xilinx Cable Drivers aren't building on the VM (but all the other Xilinx tools work). If someone is a linux guru and wants to try to make it work, contact me at [mailto:teachmeFPGA@gmail.com teachmeFPGA@gmail.com]. My next attempt is to turn the vm into a live-install and try building the cable drivers on real hardware instead of a VM.
* After loading the Xilinx settings (which will be covered in more detail when those tools are introduced), the current shell can no longer run icarus verilog flows. Start a new shell in order to run icarus verilog.
* Its a fairly minimalist system, with the FOSS tools listed above load, along with firefox, gcc and nano. Use yast or yast2 in order to install any additional packages. example yast2 --install ''packname''
* If the download link stops working, the build has likely expired on the SuseStudio server. Please email [mailto:teachmeFPGA@gmail.com teachmeFPGA@gmail.com] if the download link no longer works.
* Mad props to the susestudio team for making this possible

== Lecture ==
Lecture/Discussions will mainly be based on content from a pair of courses in MIT's Opencourseware initiative. This content is licensed on the Creative Commons Attribution NonCommercial Share-alike 3.0 license; as a result, the electronic content generated by the workshop will also need to be made available under the same license. This will allow people to freely access just the discussion slides without watching through videos. A video archive will be made available for those unable to attend.

=== List of Lectures ===
''This is currently an incomplete list, additional topics will be added as I solidify them - wgibb''
{| border="1"
|Week
|Date
|Topics Covered
|Exercise
|Solutions/Approach
|-
|1
|October 7th, 2009
|[http://wiki.hacdc.org/index.php/File:Lect1_draft2.pdf Workshop Introduction & Introduction to digital systems and design]
|Make sure people can run the Virtual Machine or FOSS tools
|Lorem Ipsum
|-
|2
|October 14th, 2009
|[http://wiki.hacdc.org/index.php/File:Lect2_draf3.pdf Boolean Logic, combinatorial circuits and timing]
|Make sure people can run the Virtual Machine or FOSS tools |[http://wiki.hacdc.org/index.php/File:Lect2_exercise.pdf Boolean & Combinatorial Exercises]
|[http://wiki.hacdc.org/index.php/File:Lect2_sol.pdf Exercise Solutions]
[[Discussion 2 Exercises Solution notes]]
|-
|3
|October 21st, 2009
|[http://wiki.hacdc.org/index.php/File:Lect3.pdf Introduction to Verilog Coding, focusing on combinatorial circuits]
|[[FPGAExercise3| Verilog Coding Modular Full Adder Design and Simulation and ALU extension project]]
|Solutions
|-
|4
|October 28th, 2009
|Make up day
|
|Solutions
|-
|4 1/2
|November 4th, 2009
|[http://wiki.hacdc.org/index.php/File:Intro_to_Sequential_Logic.pdf Introduction to Sequential Logic and Flip Flops]
|[http://projects.hacdc.org/tapemachine/SequentialCircuits.mp3 Audio]
| Placeholder
|-
|5
|November 11th, 2009
|No class meeting with Will
|[[FPGAExercise5|Different adder construction, shift register and LFSR construction]]
|[[FPGAExercise5code|4 bit counter code from group hacking session]]
|-
|6
|November 18th, 2009
|[http://wiki.hacdc.org/index.php/File:FPGAWeek6.pdf DFFs round 2, Testbenches]
[[FPGAWeek6Followup|Notes on the use of Define statements, tasks and events]]
|Shift Register & LFSR examples from week 5
|[[FPGAExercise6code|Shift Register, SR Testbench, LFSR, LFSR Testbench]]
|-
|7
|November 25th, 2009
|[[Xilinx_ISE_Installation_Instructions|Xilinx tool install party]]
|[[FPGA_Workshop#Xilinx_Links| Xilinx ISE In-Depth Tutorial]]
|See Tutorial
|-
|8
|December 2nd, 2009
|
[http://wiki.hacdc.org/index.php/File:Week8_fsm_notes.pdf Finite State Machines] 
[http://wiki.hacdc.org/index.php/File:Week8_clocking_notes.pdf Clocking Notes]
|Vending Machine Simulation from notes
|[[FPGAExercise8code|FSM level-to-pulse converter, testbench]]
|-
|9
|December 9th, 2009
|We talked about stuff
|[http://wiki.hacdc.org/index.php?title=FPGA_Workshop#FPGA_Workshop_Projects People start posting project ideas]
|[http://www.google.com/search?q=fpga+project+ideas Solutions]
|-
|10
|December 16th, 2009
|[http://wiki.hacdc.org/index.php/File:Week10_programmable_fabric.pdf Introduction to FPGAs - History, Capabilities and Features]
|Exploring designs and FPGA tools
|Solutions
|-
|10
|December 23rd, 2009
|[http://wiki.hacdc.org/index.php/File:ISE_Tutorial_for_S3E.pdf ISE Tutorial for Spartan 3E board]
|[[FPGAExercise10code | Counter Source ]]
|Video of HacDC FPGA blinkenlites
|}
 

=== Videos of Discussions ===
The videos are mpeg4 video with aac audio 
{| border="1"
| Week
| Video Links
| Notes
|-
|1
|
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV011.TOD.ff.mp4 Part 1]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV012.TOD.ff.mp4 Part 2]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV013.TOD.ff.mp4 Part 3]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV014.TOD.ff.mp4 Part 4] 
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV015.TOD.ff.mp4 Part 5]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV016.TOD.ff.mp4 Part 6]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV017.TOD.ff.mp4 Part 7]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV018.TOD.ff.mp4 Part 8]
|not equal length
|-
|2
|
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV005.TOD.ff.mp4 Part 1]
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV006.TOD.ff.mp4 Part 2]
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV007.TOD.ff.mp4 Part 3] 
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV008.TOD.ff.mp4 Part 4]
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV009.TOD.ff.mp4 Part 5]
| Video cuts out at a discussion about Rise and Fall times
|-
|3
|
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/10.avi Part 1]
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/11.avi Part 2]
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/12.avi Part 3] 
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/13.avi Part 4]
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/14.avi Part 5]
|
|-
|4
|
|
|}

== Workshop requirements ==

This workshop will be free of charge to attend, but there are additional needs in order to fully benefit from attending the workshop.
* Open mind to learning
* Willingness to read documentation, as the capacity for independent research is important for doing hardware design.
* Willingness to commit time over this fall
* Either ability to run a VMWare virtual machine, the ability to convert the VM for virtualBox, or ability to install the icarus verilog/gtkwave tools on your own. This will likely necessitate a laptop of some sort.
* Xilinx.com account, for licensing Xilinx tools and IP.
* Hardware will NOT be required at the beginning of the course but will be needed later on to run exercises and to do any interesting projects

== Workshop Frequently Asked Questions ==

# What operating systems will the FPGA toolchain be available on?
##The Xilinx ISE Webpack is supported on Windows XP Pro, Windows Vista Business, Redhat Linux and Suse Linux Enterprise. For a detailed list of official OS support, check out the [http://www.xilinx.com/ise/ossupport/index.htm Operating system support page on Xilinx.com]. The tools will run on openSuse as well. Feel free to try other linux distros and post your results.
# What is the cost of the FPGA development board we'll be using?
##The retail cost of the development board is typically around 199-220 USD, plus shipping, from a few different vendors. Links for that are [[FPGA_Workshop#Spartan_3AN_Starter_Kit|here]].
# Will there be homework?
##Since this isn't an academic course, there will not be graded homework in the traditional sense. I'll be choosing a few additional exercises that people can do outside of the workshop each week, if they wish, that will further help hone their skills.
# Will there be extensive C/C++ coding?
##C experience is not a prerequisite for this workshop. There will not be any C/C++ coding involved in the workshop directly. There is one project that I've got in mind that may be of interest to people that are proficient in C/C++ and pick up hardware design rather well.

== Workshop Mailing List ==

A HacDC Mailman mailling list has been setup for this workshop. That list is fpga@hacdc.org. You can subscribe to that list by sending an email to fpga-request@hacdc.org with the subject line "subscribe" or click the mailto link [mailto:fpga-request@hacdc.org?Subject=subscribe fpga-request@hacdc.org?Subject=subscribe] and let your email application handle it...

== Workshop Instructor ==

William Gibb, mad scientist. For contacting him regarding the workshop, please email [mailto:teachmeFPGA@gmail.com teachmeFPGA@gmail.com].

== References ==
=== Grateful Dead Trees Reference ===
Fundamentals of Digital Logic with Verilog Design by Brown and Vranesic 
Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog by Lee 
FPGA Prototyping using Verilog Examples by Chu. 
These texts will not be required for the course, but are very good launching points for the topics that we are covering.

=== Online References ===

==== General Resources ====
[http://www.opencircuitdesign.com/ Open Circuit Design] Open Source design tools 
[http://www.doulos.com/knowhow/ Doulos Digital Design Resources] Good learning and design references 
[http://www.asic-world.com/ '''ASIC World'''] Good learning references 
[http://www.play-hookey.com/digital/ Play Hookey Digital Design] Good learning references 
[http://www.fpga4fun.com/ '''FPGA4Fun''] Lots of available IP 
[http://academic.csuohio.edu/chu_p/rtl/fpga_vlog.html Companion website for Professor Pong Chu's Verilog Book] 
[http://www.opencores.org '''OpenCores'''] Very good repository for IP. Also the home to the OpenRISC System on Chip project 
[http://hdlplanet.tripod.com/verilog/verilog-manual.html#RTFToC0 Bucknell Handbook on Verilog HDL] (Martin found this) Old but useful? 
[http://verilog.openhpsdr.org/ KD7IRS's Verilog - OpenHPSDR - Lectures] Webcast style class, with lab 

==== FPGA Vendors ====
[http://www.xilinx.com/ Xilinx] 
[http://www.altera.com/ Altera] 
[http://www.actel.com/ Actel] 
[http://www.atmel.com/products/fpga/ Atmel FPGA] 
[http://www.siliconbluetech.com/ Silicon Blue] 
[http://www.latticesemi.com/ Lattice Semiconductor] 
[http://www.achronix.com/ Achronix] 

==== Course Resources ====
[http://www.icarus.com/eda/verilog/ Icaurus Verilog] 
[http://gtkwave.sourceforge.net/ GTKWave] 
[http://www.vmware.com/products/player/ VMware Player - Free download for Windows and Linux] 
[http://www.susestudio.com SUSE Studio] SLED/OpenSUSE build service. Make VMs, live installs, all customized 

==== Xilinx Links ====
[http://www.xilinx.com/support/techsup/tutorials/ Xilinx Tutorials] 
[http://www.xilinx.com/support/techsup/tutorials/tutorials10.htm Xilinx ISE 10.1 Tutorial and files] 
[http://www.xilinx.com/direct/ise10_tutorials/ise10tut.pdf ISE 10.1 In Depth Tutorial Direct link to PDF] 
[http://www.xilinx.com/support/documentation/index.htm Xilinx Documentation] This includes device data sheets, user guides, IP documentation and Xilinx software manuals 
[http://www.xilinx.com/tools/designtools.htm Xilinx Design Tools] Xilnx Software tools can be found here 
[http://www.xilinx.com/products/devkits/HW-SPAR3E-SK-US-G.htm Spatan 3E Starter Kit] Site for the Spartan 3E kit 
[http://www.xilinx.com/products/devkits/HW-SPAR3AN-SK-UNI-G.htm Spartan 3AN Starter Kit] Site for the Spartan 3AN kit 
[http://www.xilinx.com/support/training/free-courses.htm Free Video Training courses] Name says it all 
[http://xess.com/appnotes/ise-10.pdf Yet Another Xilinx ISE 10.1 Tutorial] For Xess Spartan-3 Development Board 

==== Spartan 3AN Starter Kit ====
[http://www.xilinx.com/products/devkits/HW-SPAR3AN-SK-UNI-G.htm Spartan 3AN Starter Kit] 
[http://www.em.avnet.com/evk/home/0,1707,RID%253D0%2526CID%253D45129%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html AVNet Spartan 3AN Starter Kit sales page] 
[http://www.nuhorizons.com/ NuHorizons - Xilinx Vendor] Do a search for HW-SPAR3AN-SK-UNI-G 
[http://search.digikey.com/scripts/DkSearch/dksus.dll?Cat=2621773&k=spartan%203an Digi-key Spartan 3AN Starter Kit Sales page] 
Probably also at other [[suppliers]].

===== Group Order Participants =====
NOTE: Xilinx has donated 15 spartan3 boards, which should arrive before 12/7

* Daniel (obscurite on #hacdc on freenode)
* Alden
* Dan Barlow
* Navid
* Matt Liggett
* Maitland Bottoms
* Ben Peizik (benparse@yahoo.com)
* Martin
* Rob Seastrom (rs@seastrom.com)
* Phillip Stewart
* Tim F (smilemoose@gmail.com)
* Nick
* Brian

* Elliot
* Justin

==== MIT OpenCourseWare links ====
[http://ocw.mit.edu/OcwWeb/web/terms/terms/index.htm MIT OCW Terms of Use] 
[http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-004Computation-StructuresFall2002/CourseHome/index.htm OCW site for 6.004 - Computation Structures] 
[http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-111Spring-2006/CourseHome/index.htm OCW site for 6.111 Introductory Digital Systems, 2006] 

== FPGA Workshop Projects ==
List of FPGA projects people are working on at HacDC

{|border="1"
|Person
|Project
|-
|William Gibb
|[http://opencores.org/project,spi_core_dsp_s3ean_kits AD/DA controller for Spartan 3E/3A/3AN Development Kits]
|-
|Daniel (obscurite on #hacdc on freenode)
| [[FPGAWorkshopDaniel |Daniel's Project (Game of Life w/ Martin & Breakout VGA/LED?)]]
|-
|Alden
| [[FPGAWorkshopAlden | Alden's Project]]
|-
|Dan Barlow
| [[FPGAWorkshopBarlow | Barlows's Project]]
|-
|Navid
| [[FPGAWorkshopNavid | Navid's Project]]
|-
|Matt Liggett
| [[FPGAWorkshopMatt | Matt's Project]]
|-
|Maitland Bottoms
| [[FPGAWorkshopMaitland | Maitland's Project]]
|-
|Ben Peizik (benparse@yahoo.com)
| [[FPGAWorkshopBen | Ben's Project]]
|-
|Martin
| [[FPGAWorkshopMartin | Martin's Project]]
|-
|Rob Seastrom (rs@seastrom.com)
| [[FPGAWorkshopJustin | Justin's Project]]
|-
|Phillip Stewart
| [[FPGAWorkshopPhillip | Phillip's Project]]
|-
|Tim F (smilemoose@gmail.com)
|[[FPGAWorkshopJustin | Tims Project]]
|-
|Nick
|[[FPGAWorkshopNick | Nick's Project]]
|-
|Brian
|[[FPGAWorkshopBrian | PROM Burner/Reader]]
|-
|Elliot
|[[FPGAWorkshopElliot | Elliots's Project]]
|-
|Justin
|[[FPGAWorkshopJustin | Justin's Project]]
|-
|Arc
|[[FPGAWorkshopArc | Arcs SMT oven ]]
|-
|Davel (DLotts)
|[[FPGAWorkshopDLotts | Davel's Project]]
|}

[[Category:Classes]]
[[Category:FPGAWorkshop]]

FPGA Workshop

2009-12-01T23:01:37Z

Maitland: add link to verilog.openhpsdr.org

== Main Topics ==
1) Introduction to digital logic & design 
2) Verilog HDL modeling & testing 
3) FPGA's & using them. 
 
We will be taking an approach of reviewing & learning digital design, implementing designs and methods of formally simulating and verifying designs before moving into [http://en.wikipedia.org/wiki/Field-programmable_gate_array FPGA] oriented work. This workshop will be more engineering oriented than hobbyist/tinkerer oriented.

== Hardware ==
We'll be covering some FPGA specific topics and projects using real hardware. The first half of the workshop will cover logic design, implementation and testing. This will allow people to put off ordering any hardware until they know that they actually want to pursue FPGA development, since the dev board I've chosen for this is not cheap but I feel is robust enough to be a good starting board for this group.
 
The hardware we'll be using is the Xilinx Spartan 3AN development kit. This kit is available from a few vendors for 199USD + shipping. This will be discussed more later on. The kit includes programming cable, and evaluation copies of some of the Xilinx tools."

== Tools ==

=== Verilog Simulation and Waveform Viewing ===
Icarus verilog & gtkwave; for doing Verilog compilation, simulation and waveform viewing. A makefile has been made to simplify the flow for any exercises and projects we use these tools with. That makefile can be found [[iverilogmakefile|'''here''']]. Instructions for installing these programs on Mac osX and Ubuntu can be found here: [[FOSS_Verilog_tool_installation | '''FOSS Verilog tool installation''']] 
=== FPGA Toolchain ===
After we finish up with covering Verilog modeling, we'll move to the Xilinx ISE Webpack tools and actual work with FPGAs. This software is available from Xilinx for free, and is available for Windows and Linux platforms. This will be used for Verilog compilation, simulation, synthesis of designs, design mapping, place and routing of designs, bitstream generation and board programming. Instructions for installing the Xilinx tools on the VM can be found here:[[Xilinx_ISE_Installation_Instructions | '''Xilinx ISE Installation Instructions''']] 
=== Virtual Machine ===
An OpenSuse Virtual Machine (VMWare based) will be available for people to use in this course, if they wish. This will
have the icarus verilog tools and GTKwave loaded on it, along with Firefox, gcc and make. The suseStudio team has encouraged the use of their VMs in such a manner (teaching workshops). This is being built in susestudio, and will be available as a live install as well.
 
When we move over to the Xilinx tools, people will have to download and install the Xilinx tools by themselves, since that material is copyrighted. Instructions will be given for doing that.

The VMware VM image is ready (ver 0.5.2) for people to grab if they wish. [http://susestudio.com/download/49e791d22097dd5694429fabe47ab5d2/Digital_Design__FPGA_Workshop_VM_v4.i686-0.5.2.vmx.tar.gz '''Get it here.''']

The image also works with VirtualBox. Create a new machine, and when it asks you for a hard drive, select use an existing drive. This takes you to the hard-drives list dialog box. From there, file..create a new drive, link it to the .vmdk file, select it, and you're all set. For the rest, all defaults are ok. (Bother Elliot for hints with VBox.)

There are a few items of note regarding the VM 
* Download is approximately 350MB, the tarball is about 1.5GB in size, and the virtual disk will expand up to 20gigs dynamically.
* The download link is a virgin, freshly built VM, so you'll be the first user booting it up since build.
* There are two users, root and workshop. Both have the password 'linux'
* For the user workshop, ~/scripts/ is included in their $PATH
* Also, user workshop has a few small files in ~/resources/ including a simple upcounter design example.
* May need to run the network configuration tools to ensure you get functional networking. I've experienced issues with the VM in suspend mode, switching networks on the host machine, and completely loosing network on the VM until rerunning the network config tools. They can be found poking around in the system settings for yast.
* Currently, the Xilinx Cable Drivers aren't building on the VM (but all the other Xilinx tools work). If someone is a linux guru and wants to try to make it work, contact me at [mailto:teachmeFPGA@gmail.com teachmeFPGA@gmail.com]. My next attempt is to turn the vm into a live-install and try building the cable drivers on real hardware instead of a VM.
* After loading the Xilinx settings (which will be covered in more detail when those tools are introduced), the current shell can no longer run icarus verilog flows. Start a new shell in order to run icarus verilog.
* Its a fairly minimalist system, with the FOSS tools listed above load, along with firefox, gcc and nano. Use yast or yast2 in order to install any additional packages. example yast2 --install ''packname''
* If the download link stops working, the build has likely expired on the SuseStudio server. Please email [mailto:teachmeFPGA@gmail.com teachmeFPGA@gmail.com] if the download link no longer works.
* Mad props to the susestudio team for making this possible

== Lecture ==
Lecture/Discussions will mainly be based on content from a pair of courses in MIT's Opencourseware initiative. This content is licensed on the Creative Commons Attribution NonCommercial Share-alike 3.0 license; as a result, the electronic content generated by the workshop will also need to be made available under the same license. This will allow people to freely access just the discussion slides without watching through videos. A video archive will be made available for those unable to attend.

=== List of Lectures ===
''This is currently an incomplete list, additional topics will be added as I solidify them - wgibb''
{| border="1"
|Week
|Date
|Topics Covered
|Exercise
|Solutions/Approach
|-
|1
|October 7th, 2009
|[http://wiki.hacdc.org/index.php/File:Lect1_draft2.pdf Workshop Introduction & Introduction to digital systems and design]
|Make sure people can run the Virtual Machine or FOSS tools
|Lorem Ipsum
|-
|2
|October 14th, 2009
|[http://wiki.hacdc.org/index.php/File:Lect2_draf3.pdf Boolean Logic, combinatorial circuits and timing]
|Make sure people can run the Virtual Machine or FOSS tools |[http://wiki.hacdc.org/index.php/File:Lect2_exercise.pdf Boolean & Combinatorial Exercises]
|[http://wiki.hacdc.org/index.php/File:Lect2_sol.pdf Exercise Solutions]
[[Discussion 2 Exercises Solution notes]]
|-
|3
|October 21st, 2009
|[http://wiki.hacdc.org/index.php/File:Lect3.pdf Introduction to Verilog Coding, focusing on combinatorial circuits]
|[[FPGAExercise3| Verilog Coding Modular Full Adder Design and Simulation and ALU extension project]]
|Solutions
|-
|4
|October 28th, 2009
|Make up day
|
|Solutions
|-
|4 1/2
|November 4th, 2009
|[http://wiki.hacdc.org/index.php/File:Intro_to_Sequential_Logic.pdf Introduction to Sequential Logic and Flip Flops]
|[http://projects.hacdc.org/tapemachine/SequentialCircuits.mp3 Audio]
| Placeholder
|-
|5
|November 11th, 2009
|No class meeting with Will
|[[FPGAExercise5|Different adder construction, shift register and LFSR construction]]
|[[FPGAExercise5code|4 bit counter code from group hacking session]]
|-
|6
|November 18th, 2009
|[http://wiki.hacdc.org/index.php/File:FPGAWeek6.pdf DFFs round 2, Testbenches]
[[FPGAWeek6Followup|Notes on the use of Define statements, tasks and events]]
|Shift Register & LFSR examples from week 5
|[[FPGAExercise6code|Shift Register, SR Testbench, LFSR, LFSR Testbench]]
|-
|7
|November 25th, 2009
|Xilinx tool install party
|Hello World demo
|Src for demo
|-
|8
|December 2nd, 2009
|Finite State Machines
|Practical FSM Exercise
|Solutions
|-
|9
|December 9th, 2009
|Introduction to FPGAs - History, Capabilities and Features
|Exploring designs and FPGA tools
|Solutions
|-
|10
|December 16th, 2009
|Logic Synthesis & Design considerations with FPGAs
|Conversion of projects, simulation in iSim
|Solutions
|-
|10
|December 16th, 2009
|TBD
|TBD
|TBD
|}
 

=== Videos of Discussions ===
The videos are mpeg4 video with aac audio 
{| border="1"
| Week
| Video Links
| Notes
|-
|1
|
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV011.TOD.ff.mp4 Part 1]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV012.TOD.ff.mp4 Part 2]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV013.TOD.ff.mp4 Part 3]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV014.TOD.ff.mp4 Part 4] 
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV015.TOD.ff.mp4 Part 5]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV016.TOD.ff.mp4 Part 6]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV017.TOD.ff.mp4 Part 7]
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV018.TOD.ff.mp4 Part 8]
|not equal length
|-
|2
|
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV005.TOD.ff.mp4 Part 1]
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV006.TOD.ff.mp4 Part 2]
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV007.TOD.ff.mp4 Part 3] 
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV008.TOD.ff.mp4 Part 4]
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV009.TOD.ff.mp4 Part 5]
| Video cuts out at a discussion about Rise and Fall times
|-
|3
|
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/10.avi Part 1]
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/11.avi Part 2]
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/12.avi Part 3] 
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/13.avi Part 4]
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/14.avi Part 5]
|
|-
|4
|
|
|}

== Workshop requirements ==

This workshop will be free of charge to attend, but there are additional needs in order to fully benefit from attending the workshop.
* Open mind to learning
* Willingness to read documentation, as the capacity for independent research is important for doing hardware design.
* Willingness to commit time over this fall
* Either ability to run a VMWare virtual machine, the ability to convert the VM for virtualBox, or ability to install the icarus verilog/gtkwave tools on your own. This will likely necessitate a laptop of some sort.
* Xilinx.com account, for licensing Xilinx tools and IP.
* Hardware will NOT be required at the beginning of the course but will be needed later on to run exercises and to do any interesting projects

== Workshop Frequently Asked Questions ==

# What operating systems will the FPGA toolchain be available on?
##The Xilinx ISE Webpack is supported on Windows XP Pro, Windows Vista Business, Redhat Linux and Suse Linux Enterprise. For a detailed list of official OS support, check out the [http://www.xilinx.com/ise/ossupport/index.htm Operating system support page on Xilinx.com]. The tools will run on openSuse as well. Feel free to try other linux distros and post your results.
# What is the cost of the FPGA development board we'll be using?
##The retail cost of the development board is typically around 199-220 USD, plus shipping, from a few different vendors. Links for that are [[FPGA_Workshop#Spartan_3AN_Starter_Kit|here]].
# Will there be homework?
##Since this isn't an academic course, there will not be graded homework in the traditional sense. I'll be choosing a few additional exercises that people can do outside of the workshop each week, if they wish, that will further help hone their skills.
# Will there be extensive C/C++ coding?
##C experience is not a prerequisite for this workshop. There will not be any C/C++ coding involved in the workshop directly. There is one project that I've got in mind that may be of interest to people that are proficient in C/C++ and pick up hardware design rather well.

== Workshop Mailing List ==

A HacDC Mailman mailling list has been setup for this workshop. That list is fpga@hacdc.org. You can subscribe to that list by sending an email to fpga-request@hacdc.org with the subject line "subscribe" or click the mailto link [mailto:fpga-request@hacdc.org?Subject=subscribe fpga-request@hacdc.org?Subject=subscribe] and let your email application handle it...

== Workshop Instructor ==

William Gibb, mad scientist. For contacting him regarding the workshop, please email [mailto:teachmeFPGA@gmail.com teachmeFPGA@gmail.com].

== References ==
=== Grateful Dead Trees Reference ===
Fundamentals of Digital Logic with Verilog Design by Brown and Vranesic 
Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog by Lee 
FPGA Prototyping using Verilog Examples by Chu. 
These texts will not be required for the course, but are very good launching points for the topics that we are covering.

=== Online References ===

==== General Resources ====
[http://www.opencircuitdesign.com/ Open Circuit Design] Open Source design tools 
[http://www.doulos.com/knowhow/ Doulos Digital Design Resources] Good learning and design references 
[http://www.asic-world.com/ ASIC World] Good learning references 
[http://www.play-hookey.com/digital/ Play Hookey Digital Design] Good learning references 
[http://www.fpga4fun.com/ FPGA4Fun] Lots of available IP 
[http://academic.csuohio.edu/chu_p/rtl/fpga_vlog.html Companion website for Professor Pong Chu's Verilog Book] 
[http://www.opencores.org '''OpenCores'''] Very good repository for IP. Also the home to the OpenRISC System on Chip project 
[http://hdlplanet.tripod.com/verilog/verilog-manual.html#RTFToC0 Bucknell Handbook on Verilog HDL] (Martin found this) Old but useful? 
[http://verilog.openhpsdr.org/ KD7IRS's Verilog - OpenHPSDR - Lectures] Webcast style class, with lab 

==== FPGA Vendors ====
[http://www.xilinx.com/ Xilinx] 
[http://www.altera.com/ Altera] 
[http://www.actel.com/ Actel] 
[http://www.atmel.com/products/fpga/ Atmel FPGA] 
[http://www.siliconbluetech.com/ Silicon Blue] 
[http://www.latticesemi.com/ Lattice Semiconductor] 
[http://www.achronix.com/ Achronix] 

==== Course Resources ====
[http://www.icarus.com/eda/verilog/ Icaurus Verilog] 
[http://gtkwave.sourceforge.net/ GTKWave] 
[http://www.vmware.com/products/player/ VMware Player - Free download for Windows and Linux] 
[http://www.susestudio.com SUSE Studio] SLED/OpenSUSE build service. Make VMs, live installs, all customized 

==== Xilinx Links ====
[http://www.xilinx.com/support/techsup/tutorials/ Xilinx Tutorials] 
[http://www.xilinx.com/support/techsup/tutorials/tutorials10.htm Xilinx ISE 10.1 Tutorial and files] 
[http://www.xilinx.com/direct/ise10_tutorials/ise10tut.pdf ISE 10.1 In Depth Tutorial Direct link to PDF] 
[http://www.xilinx.com/support/documentation/index.htm Xilinx Documentation] This includes device data sheets, user guides, IP documentation and Xilinx software manuals 
[http://www.xilinx.com/tools/designtools.htm Xilinx Design Tools] Xilnx Software tools can be found here 
[http://www.xilinx.com/products/devkits/HW-SPAR3E-SK-US-G.htm Spatan 3E Starter Kit] Site for the Spartan 3E kit 
[http://www.xilinx.com/products/devkits/HW-SPAR3AN-SK-UNI-G.htm Spartan 3AN Starter Kit] Site for the Spartan 3AN kit 
[http://www.xilinx.com/support/training/free-courses.htm Free Video Training courses] Name says it all 

==== Spartan 3AN Starter Kit ====
[http://www.xilinx.com/products/devkits/HW-SPAR3AN-SK-UNI-G.htm Spartan 3AN Starter Kit] 
[http://www.em.avnet.com/evk/home/0,1707,RID%253D0%2526CID%253D45129%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html AVNet Spartan 3AN Starter Kit sales page] 
[http://www.nuhorizons.com/ NuHorizons - Xilinx Vendor] Do a search for HW-SPAR3AN-SK-UNI-G 
[http://search.digikey.com/scripts/DkSearch/dksus.dll?Cat=2621773&k=spartan%203an Digi-key Spartan 3AN Starter Kit Sales page] 
Probably also at other [[suppliers]].

===== Group Order Participants =====
* Daniel (obscurite on #hacdc on freenode)
* Alden
* Dan Barlow
* Navid
* Matt Liggett
* Maitland Bottoms
* Ben Peizik (benparse@yahoo.com)
* Martin
* Rob Seastrom (rs@seastrom.com)
* Phillip Stewart
* Tim F (smilemoose@gmail.com)
* Nick
* Brian (bpbri [at] hotmail.com)
* Elliot
* Justin

==== MIT OpenCourseWare links ====
[http://ocw.mit.edu/OcwWeb/web/terms/terms/index.htm MIT OCW Terms of Use] 
[http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-004Computation-StructuresFall2002/CourseHome/index.htm OCW site for 6.004 - Computation Structures] 
[http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-111Spring-2006/CourseHome/index.htm OCW site for 6.111 Introductory Digital Systems, 2006] 

[[Category:Classes]]
[[Category:FPGAWorkshop]]

Xilinx ISE Installation Instructions

2009-11-25T15:38:38Z

Maitland: amd64 and nexys2prog notes

== ISE Installation Instructions ==
# Make sure you have a xilinx.com account
# Go to Xilinx.com, navigate to their ISE Webpack download page. Links can be found here [http://www.xilinx.com/tools/webpack.htm '''ISE Webpack''']
# Once you sign in and register, you'll be at the Xilinx Entitlement center, and have several options to download software. On your left, under quick links, there is a link titled "Register and Download 10.1 and earlier software."
## You will receive a registration email. This will contain a registrationID which you'll need later. Save this email and keep it handy.
# Follow the screens to download the ISE Webpack. You'll be presented with either downloading the 2.5Gb image or the Webinstall client, which will download the files you'll need as it installs. You can choose either, I would recommend grabbing the 2.25Gb tarball. Instructions will be based on installing from the full tarball. Expect your vm drive to start growing.
# By default, your download (webpack_SFD.tar for the full file) will go to your ~/Desktop folder. Open up a terminal and unpack the tarball.
##<pre> cd ~/Desktop </pre>
## <pre>tar -xvf webpack_SFD.tar </pre>
##This creates the directory ~/Desktop/webpack containing the installation files for the webpack. These installation files will work for '''Linux''' and '''Windows'''.
# Now we're going to run the installer as root
##<pre> cd webpack </pre>
##<pre> su (password is linux on the vm) </pre>
##<pre> ./setup </pre>
# During the setup you'll be prompted for a registrationID. This is the registrationID in the email you got back in step 3. Enter it here.
# You'll then be presented with terms of service screens. Agree through them to proceed.
# Next you'll be presented with a choice of installation directory. The default choise, /opt/Xilinx/10.1 is fine
# Next is installation options You may as well choose all of them, but you must choose "All FPGA devices except Virtex 4 and Virtex 5" in order to design towards the Spartan 3E boards. You should be ready for your VM's disk to grow by 4 more gigs.
# You'll then be presented with a set of environmental variables which are set in a settings file for ise. They can be left at defaults.
# Select the cable drivers. Click through to confirm the settings and install the tools.
## You may uncheck the update feature, if you do not wish to immeadiately update the tools after installation. This will cause a large download to occur after installation, if it is checked.
# Wait for the tools to install. Play cards with a buddy.
# If you let XilinxUpdate run after installation, it will start up, and you'll need to tell it you want to download and install the 1.5gb of updates. Find a buddy and play cards.
# The cable drivers will fail to build. A solution for this is forthcoming (just need to test it).
# You can remove the folder from your desktop. You may want to keep the tarball around if you need to reinstall.
## <pre> exit </pre> To get out of su
## <pre> rm -rf ./webpack </pre>

 
==Running the tools==
# Open up a terminal and type the following commands
## <pre> cd /opt/Xilinx/10.1/ISE </pre>
## <pre> source settings32.sh </pre>
## <pre> ise </pre>
# You will now have launched Xilinx ISE.
## If this is your first time using Xilinx ISE, you should go through the in-depth tutorial linked to on the [[FPGA_Workshop#Xilinx_Links|mainpage]].

==64 bit install==

If the Xilinx ISE Webpack install file complains about not supporting your 64-bit computer:

The installer is just a shell script, edit out the test.

Since ISE is a 32-bit application, you'll need 32-bit libraries on your 64-bit system.
`apt-get install ia32-libs` or equivalent for you distribution to get them. (Debian
'Lenny' doesn't have libuuid in its ia32-libs package. You'll have to scrounge those files
up from the i386 libuuid1 package yourself. More recently libuuid is included in ia32-libs,
so this wont be a problem in Debian 'Squeeze' and later.) Your 64-bit amd64 box will run
32-bit i386 binaries just fine.

Run the installer script. Things will work just fine.

==Alternative to Digilent Adept Suite==

Some basics:

USB cable plugged into laptop. With the Power Select jumper
in the USB position, turning on the power switch lights the
red power LED. With the Mode jumper on ROM, the board will
load the demo code from ROM and light up the 7-segment LED
displays and the switches will turn on and off the other LEDs.
The Yellow Done LED lights when the load completes.

With the Mode jumper in the JTAG position the board starts up
waiting for JTAG data. Yes, there is a JTAG cable header,
but this setting also works for the USB JTAG interface.

A fine bit of clue: [http://www.edaboard.com/ftopic345414.html '''Programming Digilent Nexys 2 from Linux'''] 

That leads to the good stuff in
[http://plausible.org/andy/nexys2prog.tar.gz '''nexys2prog.tar.gz''']
(Note: UrJTAG is already in a Debian package
[http://packages.debian.org/squeeze/urjtag])
This allows one to avoid needing to use the "Digilent Adept Suite",
and thus, Windows.

The one can use the Xilinx ISE Webpack to convert some example
verilog source files into a .bit file, then use the
nexys2prog to load the board with that .bit file.
Can even be done on a Debian laptop where the only non-free
software is the Xilinx ISE Webpack..

Just hit the reset button, and the board is ready to get
another bitfile load, run nexys2prog and reconfigure the
hardware on the fly.

[[Category:FPGAWorkshop]]